This page covers the hardware reference. For the philosophy and the right-to-repair context behind it, see the Open Source Overview.
¶ Linux Kernel
The Defend-O-Tron incorporates a custom Linux kernel and drivers. It's built on the Armbian 64-bit platform, which uses Debian as the base operating system. Every layer of the software stack is open source: the kernel and the device tree, the system services, the defense components (CrowdSec, Suricata, AdGuard Home), the management interface (Cockpit), and the dashboard stack (Grafana, Victoria Metrics). If you want to audit it, you can. If you want to fork it, you can.
¶ AI Inference (NPU)
The Defend-O-Tron V100 includes a Neural Processing Unit on-die — the Rockchip RK3568B2's built-in 0.8 TOPS NPU. It's modest compared to data-center accelerators, but it's standard hardware accessible through Rockchip's open RKNN Toolkit — the same software the rest of the Rockchip SBC community uses.
¶ What 0.8 TOPS actually buys you
- 3–5× speedup over CPU on common CNN inference workloads (object detection, classification, anomaly detection), with roughly 30% lower power draw compared to running the same model on the CPU cores.
- Real-time inference for small-to-mid-sized models — voice recognition, image classification, network-traffic anomaly classifiers.
- Standard AI frameworks — Caffe, TensorFlow, TF-Lite, ONNX, and PyTorch models can be converted to the RKNN runtime format and executed on the NPU.
¶ What the Defend-O-Tron does with the NPU today
Nothing, yet. The current shipped firmware doesn't use the NPU — the device's defense relies on rule-based IDS (Suricata + CrowdSec) running entirely on the CPU. The NPU is hardware we're characterizing for future use, primarily for two roadmap directions:
- Network anomaly detection. Lightweight classifier models running on the NPU could flag traffic patterns the rule-based IDS misses — and do so without the latency overhead of forwarding traffic to a cloud service.
- Local LLM-assisted log analysis. Small specialist models can summarize and triage event streams on-device — a capability that today typically requires either dedicated GPU hardware or paid cloud-API calls.
The V200 platform (Radxa E54C, in development) targets a 5 TOPS NPU — roughly six times the V100's capacity, enough to run 1.5B-parameter LLMs locally per Radxa's documentation. That hardware is the headroom we'd build serious AI-assisted defense features against.
The V100's NPU is always-on hardware that runs no inference workload by default. When we eventually ship NPU-based defense features, the resource impact will be documented and individual operators will be able to disable AI-assisted analysis if they prefer.
¶ Datasheets
Rockchip SOC 3658-B2 A bit of lite reading¶ Schematics
Currently our hardware is a reference desgin built on the NanoPi R5s LTS platform.
Defend-O-Tron Schematic For the electronics enthusiast¶ Board Layout
PCB: 8 Layer, 62x90x1.6mm
¶ Bottom Layer with pads and silkscreen
¶ Top Layer with pads and silkscreen
¶ Pin Connections
- 12-pin GPIO
| Pin # | GPIO | SPI | UART | PWM | POWER | Description |
|---|---|---|---|---|---|---|
| 1 | VCC3V3_SYS | 3.3v | power output | |||
| 2 | VCC3V3_SYS | 3.3V | power output | |||
| 3 | GPIO3_C3 | SPI1_CLK_M1 | UART5_RX_M1 | 3.3V | level | |
| 4 | GND | |||||
| 5 | GPIO3_C2 | SPI1_MISOI_M1 | UART5_TX_M1 | 3.3V | level | |
| 6 | GPIO3_A1 | SPI1_CS0_M1 | 3.3V | level | ||
| 7 | GPIO3_C1 | SPI1_MOSI_M1 | 3.3V | level | ||
| 8 | GND | |||||
| 9 | GPIO4_C5 | UART9_TX_M1 | PWM12_M1 | 3.3V | level | |
| 10 | GPIO4_C6 | UART9_RX_M1 | PWM13_M1 | 3.3V | level | |
| 11 | GPIO3_C4 | UART7_TX_M1 | PWM14_M0 | 3.3V | level | |
| 12 | GPIO3_C5 | UART7_RX_M1 | PWM15_IR_M0 | 3.3V | level | |
- 2x8-pin SDIO/I2S
| Pin # | PIO | SD/MMC/SDIO | I2S | POWER | Description |
|---|---|---|---|---|---|
| 1 | VCC5V0_SYS | 5V | power output | ||
| 2 | VCC5V0_SYS | 5V | power output | ||
| 3 | GPIO3_C6 | SDMMC2_D0_M0 | I2S1_MCLK_M1 | 1.8V | level |
| 4 | GPIO3_C7 | SDMMC2_D1_M0 | I2S1_SCLK_TX_M1 | 1.8V | level |
| 5 | GND | ||||
| 6 | GND | ||||
| 7 | GPIO3_D0 | SDMMC2_D2_M0 | I2S1_LRCK_TX_M1 | 1.8V | level |
| 8 | GPIO3_D3 | SDMMC2_CLK_M0 | I2S1_SDI1_M1 | 1.8V | level |
| 9 | GND | ||||
| 10 | GND | ||||
| 11 | GPIO3_D1 | SDMMC2_D3_M0 | I2S1_SDO0_M1 | 1.8V | level |
| 12 | GPIO3_D2 | SDMMC2_CMD_M0 | I2S1_SDI0_M1 | 1.8V | level |
| 13 | GND | ||||
| 14 | GND | ||||
| 15 | GPIO3_D5 | SDMMC2_PWREN_M0 | I2S1_SDI3_M1 | 1.8V | level |
| 16 | GPIO3_D4 | SDMMC2_DET_M0 | I2S1_SDI2_M1 | 1.8V | level |
- Debug UART Pin Spec
3.3V level signals, 1500000bps
| Pin # | Assignment | Description |
|---|---|---|
| 1 | GND | 0V |
| 2 | UART2DBG_TX | output |
| 3 | UART2DBG_RX | input |
-
USB Port
Each USB 3.2 Gen 1 port has 1.4A overcurrent protection. -
RTC
RTC backup current is 0.25μA TYP (VDD =3.0V, TA =25℃).
Connector P/N: Molex 53398-0271